The H7 can provide a XVLCK at any freq you need, an I2C bus, a SPI bus, and it has an 8-bit DCMI interface that takes 8-bits in parallel with a PCLK to latch the bits and HREF and VSYNC inputs. Only the HREF is really important to tell the logic when to accept pixels and when to ignore. However, you can technically configure the hardware to accept pixels on every PCLK edge.
Um, anyway, it looks like the first chip needs an LVDS receiver. So, it needs an FPGA. However, a simple lattice MachX03 would be enough to do the LVDS to parallel conversion. In fact, they have IP available for that too. Sony subLVDS to Parallel Bridge - Lattice Semiconductor
The second camera is USB3.0 only.